Career & Experience

This is very high-level overview of my past and current roles as an engineer.

Contact

Email: joserubengarciamatos@gmail.com

Email_GitHub: jg-fossh@protonmail.com

LinkedIn: https://linkedin.com/in/josé-garcía-b126b0a6

GitHub: https://github.com/jg-fossh

Website: http://jg-fossh.github.io

Experience

Architect - Embedded Logic & Firmware

ASML at Wilton, CT | August 2023 - PRESENT

Develop and implement architecture and technology road-maps for hardware(FPGA Logic) to improve commonality and scale-ability in both designs and verification.

Sr. Design Engineer - Embedded Logic & Firmware

ASML at Wilton, CT | November 2021 - August 2023

Multiple projects from high speed communication protocols for image transfer and reticle cleanliness analysis to machine damage control logic to prevent downtime of lithography machine and robotics at multiple stages.

Hardware Engineer - Logic Design & Verification

L3Harris at Mason, OH | March 2018 - November 2021

Developed space application logic design for radio transmitters, all the way from lower modules, design sign-off and lab integration.

Software Validation Engineer

Honeywell Aerospace at Aguadilla, PR | May 2017 - March 2018

Verified commercial and military aircraft display systems using automated test frameworks, executed software verification plans, improving test coverage.

Hardware Engineer - FPGA Logic Design

Honeywell Aerospace at Aguadilla, PR | March 2014 - May 2017

Developed lower modules for communication interfaces for central telemetry units that interconnected different protocols. Also developed UVM test benches and verification agents for individual modules and integrated designs.

Education

B.Sc. in Electrical Engineering

University of Puerto Rico - Mayaguez, PR | August 2007 - December 2013

Skills

  • Verilog
  • UVM
  • VHDL
  • Embedded Systems
  • Python
  • FPGA Design
  • Digital Signal Processing
  • MATLAB
  • Verilator
  • CoCoTB